Kazuki Monta will present research conducted at Kobe University at the 2025 Symposium on VLSI Technology and Circuits, to be held in Kyoto, on June 11, 2025.
Presentation Title:
"A High-Order Masking with Load-Delay-Equalized WDDL for Provable Side-Channel Security"
This research proposes an approach that enhances the resistance of cryptographic circuits against high-order side-channel attacks by combining circuit-level hiding techniques with advanced algorithm-level masking methods, aiming to achieve more practical and robust security designs.
Symposium on VLSI Technology and Circuits 
